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19-4349; Rev 0; 10/08
16-Bit Mono Audio Voice Codec
General Description
The MAX9860 is a low-power, voiceband, mono audio codec designed to provide a complete audio solution for wireless voice headsets and other mono voice audio devices. Using an on-chip bridge-tied load mono headphone amplifier, the MAX9860 can output 30mW into a 32 earpiece while operating from a single 1.8V power supply. Very low power consumption makes it an ideal choice for battery-powered applications. The MAX9860's flexible clocking circuitry utilizes common system clock frequencies ranging from 10MHz to 60MHz, eliminating the need for an external PLL and multiple crystal oscillators. Both the ADC and DAC support sample rates of 8kHz to 48kHz in either synchronous or asynchronous operation. Both master and slave timing modes are supported. Two differential microphone inputs are available with a user-programmable preamplifier and programmable gain amplifier. Automatic gain control with selectable attack/release times and signal threshold allows maximum dynamic range. A noise gate with selectable threshold provides a means to quiet the channel when no signal is present. Both the DAC and ADC digital filters provide full attenuation for out-of-band signals as well as a 5th order GSM-compliant digital highpass filter. A digital side tone mixer provides loopback of the microphones/ADC signal to the DAC/headphone output. Serial DAC and ADC data is transferred over a flexible digital I2S-compatible interface that also supports TDM mode. Mode settings, volume control, and shutdown are programmed through a 2-wire, I2C-compatible interface. The MAX9860 is fully specified over the -40C to +85C extended temperature range and is available in a lowprofile, 4mm x 4mm, 24-pin thin QFN package. 1.8V Single-Supply Operation Digital Highpass Elliptical Filters with Notch for 217Hz (GSM) Mono 30mW BTL Headphone Amplifier Dual Low-Noise Microphone Inputs Automatic Microphone Gain Control and Noise Gate 90dB DAC DR (fS = 48kHz) 81dB ADC DR (fS = 48kHz) Supports Master Clock Frequencies from 10MHz to 60MHz Supports Sample Rates from 8kHz to 48kHz Flexible Digital Audio Interface Clickless/Popless Operation 2-Wire, I2C-Compatible Control Interface Available in 24-Pin, Thin QFN, 4mm x 4mm x 0.8mm Package
Features
MAX9860
Ordering Information
PART MAX9860ETG+ TEMP RANGE -40C to +85C PIN-PACKAGE 24 TQFN-EP*
+Denotes a lead-free/RoHS-compliant package. *EP = Exposed pad.
Simplified Block Diagram
DVDDIO 1.7V TO 3.6V AVDD AND DVDD 1.7V TO 1.9V
Applications
Audio Headsets Portable Navigation Device Mobile Phones Smart Phones VoIP Phones Audio Accessories
DIGITAL AUDIO INPUT/OUTPUT
I2C INTERFACE
MAX9860
DAC
DIGITAL AUDIO INTERFACE
DIGITAL FILTERING AND MIXERS
ADC
DIFF MIC DIFF MIC
CLOCK CONTROL
ADC
Pin Configuration and Typical Operating Circuit appear at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
16-Bit Mono Audio Voice Codec MAX9860
ABSOLUTE MAXIMUM RATINGS
(Voltages referenced to AGND.) DVDDIO, SDA, SCL, IRQ.......................................-0.3V to +3.6V AVDD, DVDD............................................................-0.3V to +2V AGND, DGND, MICGND .......................................-0.3V to +0.3V OUTP, OUTN, PREG, REF, MICBIAS ......-0.3V to (AVDD + 0.3V) MICLP, MICLN, MICRP, MICRN, REG ....-0.3V to (PREG + 0.3V) MCLK, LRCLK, BCLK, SDOUT, SDIN..................................-0.3V to (DVDDIO + 0.3V) Continuous Power Dissipation (TA = +70C) 24-Pin TQFN (derate 27.8mW/C above +70C, multilayer board) ......................................................2222mW Junction-to-Ambient Thermal Resistance (JA) (Note 1) 24-Pin TQFN (derate 27.8mW/C above +70C, multilayer board) ........................................................36C/W Operating Temperature Range ...........................-40C to +85C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
ELECTRICAL CHARACTERISTICS
(VAVDD = VDVDD = VDVDDIO = +1.8V, RL = , headphone load (RL) connected between OUTP and OUTN, CREF = 2.2F, CMICBIAS = CPREG = CREG = 1F, AVPRE = +20dB, AVMICPGA = 0dB, MCLK = 13MHz, LRCLK = 8kHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 2)
PARAMETER SYMBOL CONDITIONS AVDD (inferred from HP output PSRR) Supply Voltage Range DVDD (inferred from codec performance tests) DVDDIO DAC playback mode (48kHz) Full operation 8kHz mono ADC + DAC IAVDD+DVDD Full operation 8kHz stereo ADC + DAC Stereo ADC only (48kHz) AVDD DVDD AVDD DVDD AVDD DVDD AVDD DVDD AVDD Shutdown Supply Current Shutdown to Full Operation DAC (Note 4) Gain Error Dynamic Range (Note 5) DAC Full-Scale Output DAC Path Phase Delay f = 1kHz, 0dBFS, HP filter disabled, digital input to analog output THD+N fS = 8kHz fS = 16kHz DR +0dB volume setting, fS = 8kHz, measured at headphone output, TA = +25C 84 ISHDN TA = +25C DVDD + DVDDIO MIN 1.7 1.7 1.7 TYP 1.8 1.8 1.8 1.46 1.05 4.08 0.78 6.17 0.8 5.38 1.68 0.56 1.65 10 1 90 1 1.2 ms 0.59 -87 dB 5 MAX 1.9 1.9 3.6 2.2 1.6 5.7 1.0 9.0 1.2 8.0 2.2 5 5 A ms % dB VRMS mA V UNITS
Total Supply Current (Note 3)
Total Harmonic Distortion + Noise
f = 1kHz, MCLK = 12.288MHz, LRCLK = 48kHz
2
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16-Bit Mono Audio Voice Codec
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VDVDD = VDVDDIO = +1.8V, RL = , headphone load (RL) connected between OUTP and OUTN, CREF = 2.2F, CMICBIAS = CPREG = CREG = 1F, AVPRE = +20dB, AVMICPGA = 0dB, MCLK = 13MHz, LRCLK = 8kHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 2)
PARAMETER SYMBOL CONDITIONS f = 1kHz, VRIPPLE = 100mVP-P, AVPGA = 0dB f = 10kHz, VRIPPLE = 100mVP-P, AVPGA = 0dB DAC LOWPASS DIGITAL FILTER Passband Cutoff Passband Ripple Stopband Cutoff Stopband Attenuation DAC HIGHPASS DIGITAL FILTER DVFLT = 0x1 (elliptical for 16kHz GSM) DVFLT = 0x2 (500Hz Butterworth for 16kHz) 5th Order Passband Cutoff (-3dB from Peak, I2C Register Programmable) (Note 6) fDHPPB DVFLT = 0x3 (elliptical for 8kHz GSM) DVFLT = 0x4 (500Hz Butterworth for 8kHz) DVFLT = 0x5 (200Hz Butterworth for 48kHz) DVFLT = 0x1 (elliptical for 16kHz GSM) DVFLT = 0x2 (500Hz Butterworth for 16kHz) 5th Order Stopband Cutoff (-30dB from Peak, I2C Register Programmable) (Note 6) fDHPSB DVFLT = 0x3 (elliptical for 8kHz GSM) DVFLT = 0x4 (500Hz Butterworth for 8kHz) DVFLT = 0x5 (200Hz Butterworth for 48kHz) DC Blocking ADC Full-Scale Input Voltage Channel Gain Mismatch 0dBFS Differential MIC Input, AVPRE = 0dB, AVPGA = 0dB 1 0.3 VP-P % DCAtten DVFLT 0x0 0.0161 x fS 0.0312 x fS 0.0321 x fS 0.0625 x fS 0.0042 x fS 0.0139 x fS 0.0156 x fS 0.0279 x fS 0.0312 x fS 0.0021 x fS 90 dB Hz Hz fSLP fPLP With respect to fS within ripple; fS = 8kHz to 48kHz -3dB cutoff f < fPLP With respect to fS; fS = 8kHz to 48kHz f > fSLP, f = 20Hz to 20kHz 0.448 x fS 0.451 0.1 0.476 x fS 75 Hz fS dB Hz dB MIN TYP 94 dB 71 MAX UNITS
MAX9860
Power-Supply Rejection Ratio
PSRR
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3
16-Bit Mono Audio Voice Codec MAX9860
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VDVDD = VDVDDIO = +1.8V, RL = , headphone load (RL) connected between OUTP and OUTN, CREF = 2.2F, CMICBIAS = CPREG = CREG = 1F, AVPRE = +20dB, AVMICPGA = 0dB, MCLK = 13MHz, LRCLK = 8kHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 2)
PARAMETER Dynamic Range (Note 5) SYMBOL DR CONDITIONS fS = 8kHz, AVPRE = 0dB, A-weighted from 20Hz to fS/2 fS = 48kHz, AVPRE = 0dB, TA = +25C ADC Phase Delay Total Harmonic Distortion THD f = 1kHz, 0dBFS, HP filter disabled, analog input to digital output fS = 8kHz fS = 16kHz -70 75 MIN TYP 81 83 1.2 ms 0.61 -75 82 dB 76 -92 0.445 x fS 0.449 0.1 0.469 x fS 74 0.0161 x fS 0.0312 x fS 0.0321 x fS 0.0625 x fS 0.0042 x fS Hz dB dB MAX UNITS dB
f = 1kHz, fS = 48kHz, TA = +25C f = 1kHz, VRIPPLE = 100mVP-P, AVPGA = 0dB f = 10kHz, VRIPPLE = 100mVP-P, AVPGA = 0dB
Power-Supply Rejection Ratio
PSRR
Channel Crosstalk ADC LOWPASS DIGITAL FILTER Passband Cutoff Passband Ripple Stopband Cutoff Stopband Attenuation ADC HIGHPASS DIGITAL FILTER fSLP fPLP
Driven channel at -1dBFS, f = 1kHz With respect to fS within ripple; fS = 8kHz to 48kHz -3dB cutoff f < fPLP With respect to fS; fS = 8kHz to 48kHz f > fSLP
Hz fS dB Hz dB
AVFLT = 0x1 (elliptical for 16kHz GSM) AVFLT = 0x2 (500Hz Butterworth for 16kHz) 5th Order Passband Cutoff (-3dB from Peak, I2C Register Programmable) (Note 6) fAHPPB AVFLT = 0x3 (elliptical for 8kHz GSM) AVFLT = 0x4 (500Hz Butterworth for 8kHz) AVFLT = 0x5 (200Hz Butterworth for 48kHz)
4
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16-Bit Mono Audio Voice Codec
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VDVDD = VDVDDIO = +1.8V, RL = , headphone load (RL) connected between OUTP and OUTN, CREF = 2.2F, CMICBIAS = CPREG = CREG = 1F, AVPRE = +20dB, AVMICPGA = 0dB, MCLK = 13MHz, LRCLK = 8kHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 2)
PARAMETER SYMBOL CONDITIONS AVFLT = 0x1 (elliptical for 16kHz GSM) AVFLT = 0x2 (500Hz Butterworth for 16kHz) 5th Order Stopband Cutoff (-30dB from peak, I2C Register Programmable) (Note 6) fAHPSB AVFLT = 0x3 (elliptical for 8kHz GSM) AVFLT = 0x4 (500Hz Butterworth for 8kHz) AVFLT = 0x5 (200Hz Butterworth for 48kHz) DC Blocking CLOCKING MCLK Input Frequency MCLK Duty Cycle Maximum MCLK Input Jitter LRCLK Data Rate Frequency LRCLK PLL Lock Time LRCLK Acceptable Jitter for Maintaining PLL Lock MONO HEADPHONE AMPLIFIER Output Power Total Harmonic Distortion + Noise Dynamic Range (Note 5) POUT THD+N DR f = 1kHz, THD+N 1% TA = +25C RL = 16 RL = 32 30 50 33 0.05 0.08 90 60 84 86 71 0.25 RL = 32 RL = 500 100 -70 1 mV pF dBV dB mW % dB For guaranteed performance limits 8 12 20 DCATTEN AVFLT 0x0 MCLK is not required to be synchronous or related to the desired LRCLK data rate MIN TYP 0.0139 x fS 0.0156 x fS 0.0279 x fS 0.0312 x fS 0.0021 x fS 90 dB Hz MAX UNITS
MAX9860
10 40 50 100
60 60 48 25
MHz % psRMS kHz ms ns
RL = 32, POUT = 25mW, f = 1kHz RL = 16, POUT = 25mW, f = 1kHz +0dB volume setting, DAC input at fS = 8kHz to 48kHz AVDD = 1.7V to 1.9V VRIPPLE = 100mVP-P, f = 217Hz VRIPPLE = 100mVP-P, f = 20kHz VOUTP - VOUTN, TA =+25C No sustained oscillations
Power-Supply Rejection Ratio Output Offset Voltage Capacitive Drive Capability Click-and-Pop Level
PSRR VOS
Peak voltage into/out of shutdown, 32sps, A-weighted
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5
16-Bit Mono Audio Voice Codec MAX9860
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VDVDD = VDVDDIO = +1.8V, RL = , headphone load (RL) connected between OUTP and OUTN, CREF = 2.2F, CMICBIAS = CPREG = CREG = 1F, AVPRE = +20dB, AVMICPGA = 0dB, MCLK = 13MHz, LRCLK = 8kHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 2)
PARAMETER MICROPHONE AMPLIFIER PAM = 00 Preamplifier Gain AVPRE TA = +25C PAM = 01 PAM = 10 PAM = 11 MIC PGA Gain MIC PGA Gain Step Size Common-Mode Rejection Ratio MIC Input Resistance MIC Input Bias Voltage AVPRE = 0dB, AVMICPGA = 0dB, VIN = 1VP-P, f = 1kHz AVPRE = +30dB, AVMICPGA = 0dB, VIN = 31mVP-P, f = 1kHz AVDD = 1.7V to 1.9V PSRR VRIPPLE = 100mV at 1kHz, input referred VRIPPLE = 100mV at 10kHz, input referred VMICBIAS ILOAD = 1mA, TA = +25C ILOAD = 1mA to 2mA LRR VRIPPLE = 100mVP-P at 217Hz VRIPPLE = 100mVP-P at 10kHz A-weighted AGCHLD[1:0] setting range, FREQ 0 AGCATK[1:0] setting range, FREQ 0 AGCRLS[2:0] setting range, FREQ 0 AGCSTH[3:0] setting range, FREQ 0 50 3 0.078 -3 0.5 -72 4 0 DVST PDLY 2dB steps MIC input to headphone output, f = 1kHz, HP filter disabled 8kHz 16kHz -60 2.2 ms 1.1 12 0 -16 1.5 60 CMRR RIN_MIC VIN = 100mVP-P at 217Hz All gain settings, measured at MICLN/MICRN 30 0.7 AVMICPGA PGAM = 0x14-0x1F PGAM = 0x00 -0.5 19 29 Off 0 20 30 0 +20 1 50 50 0.8 -75 -66 95 82 76 1.55 0.2 82 81 9.5 400 200 10 -18 1.6 10 0.9 +0.5 21 31 dB dB dB k V dB dB dB dB dB V mV dB dB VRMS ms ms s dB s dB dB dB dB dB SYMBOL CONDITIONS MIN TYP MAX UNITS
Total Harmonic Distortion + Noise
THD+N
MIC Power-Supply Rejection Ratio MICROPHONE BIAS MICBIAS Output Voltage Load Regulation MICBIAS Line Ripple Rejection MICBIAS Noise Voltage AUTOMATIC GAIN CONTROL AGC Hold Duration AGC Attack Time AGC Release Time AGC Threshold Level NOISE GATE NG Attack and Release Time NG Threshold Level Noise Gate Threshold Step Size NG Attenuation DIGITAL SIDETONE Sidetone Gain Adjust Sidetone Phase Delay
6
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16-Bit Mono Audio Voice Codec
DIGITAL AUDIO INTERFACE ELECTRICAL CHARACTERISTICS
(VDVDD = VDVDDIO = 1.8V, unless otherwise noted.) (Note 2)
PARAMETER BCLK Cycle Time BCLK High Time BCLK Low Time BCLK or LRCLK Rise and Fall Time SDIN or LRCLK to BCLK Rising Setup Time SDIN or LRCLK to BCLK Falling Setup Time SDIN or LRCLK to BCLK Rising Hold Time SDIN or LRCLK to BCLK Falling Hold Time SDOUT Delay Time from BCLK Rising Edge SYMBOL tBCLKS tBCLKH tBCLKL tR , tF tSU tSU tHD tHD tDLY CONDITIONS Slave operation Slave operation Slave operation Master operation ABCI = DBCI = 0 ABCI = DBCI = 1 ABCI = DBCI = 0 ABCI = DBCI = 1 ABCI = DBCI = 0, CL = 30pF 25 25 0 0 0 40 MIN 75 30 30 7 TYP MAX UNITS ns ns ns ns ns ns ns ns ns
MAX9860
I2C INTERFACE ELECTRICAL CHARACTERISTICS
(VDVDD = VDVDDIO = 1.8V, unless otherwise noted.) (Note 2)
PARAMETER Serial-Clock Frequency Bus Free Time Between STOP and START Conditions Hold Time (Repeated) START Condition SCL Pulse Width Low SCL Pulse Width High Setup Time for a Repeated START Condition Data Hold Time Data Setup Time SDA and SCL Receiving Rise Time SDA and SCL Receiving Fall Time SYMBOL fSCL tBUF tHD,STA tLOW tHIGH tSU,STA tHD,DAT tSU,DAT tR tF CB is in pF CB is in pF CONDITIONS MIN 0 1.3 0.6 1.3 0.6 0.6 0 100 20 + 0.1CB 20 + 0.1CB 300 300 900 TYP MAX 400 UNITS kHz s s s s s ns ns ns ns
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16-Bit Mono Audio Voice Codec MAX9860
I2C INTERFACE ELECTRICAL CHARACTERISTICS (continued)
(VDVDD = VDVDDIO = 1.8V, unless otherwise noted.) (Note 2)
PARAMETER SDA Transmitting Fall Time Setup Time for STOP Condition Bus Capacitance Pulse Width of Suppressed Spike SYMBOL tF tSU,STO CB tSP 0 0.7 x DVDDIO 0.3 x DVDDIO 1.4 0.4 IIH, IIL TA = +25C -1 3 0.7 x DVDD 0.3 x DVDD 200 IIH, IIL TA = +25oC -1 3 VOL VOH IOL = 3mA IOL = 3mA DVDDIO - 0.4 -1 +1 0.4 0.4 +1 +1 CB is in pF CONDITIONS MIN TYP MAX 250 UNITS ns s 400 50 pF ns
20 + 0.1CB 0.6
DIGITAL INPUTS (LRCLK, BCLK, SDIN, MCLK) Input Voltage High Input Voltage Low MCLK Input Voltage High MCLK Input Voltage Low Input Leakage Current Input Capacitance DIGITAL INPUTS (SCL, SDA) Input Voltage High Input Voltage Low Input Hysteresis Input Leakage Current Input Capacitance CMOS DIGITAL OUTPUTS (BCLK, LRCLK, SDOUT) Output Low Voltage Output High Voltage V V VIH VIL V V mV A pF VIH VIL V V V V A pF
OPEN-DRAIN DIGITAL OUTPUTS (SDA, IRQ) Output High Leakage Current Output Low Voltage IOH VOL VOUT = DVDDIO, TA = +25C IOL = 3mA A V
Note 2: All devices are 100% production tested at room temperature. All temperature limits are guaranteed by design. Note 3: Supply current measurements taken with no applied signal at microphone inputs. A digital zero audio signal used for all digital serial audio inputs. Headphone outputs are loaded as stated in the global conditions. Note 4: DAC performance is measured at headphone outputs. Note 5: ADC, DAC, and headphone amplifier dynamic ranges are measured using the EIAJ method. -60dBV 1kHz input signal, A-weighted and normalized to 0dBFS. Note 6: Notch for GSM filters occurs at 217Hz.
8
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16-Bit Mono Audio Voice Codec
Typical Operating Characteristics
(VAVDD = +1.8V, VDVDD = VDVDDIO = +1.8V, RL = , headphone load (RL) connected between OUTP and OUTN, CREF = 2.2F, CPREG = CREG = 1F, CMICBIAS = 1F AVMICPGA = 0dB, AVPRE = +20dB, MCLK = 13MHz, TA = +25C, unless otherwise noted.)
TOTAL HARMONIC DISTORTION + NOISE vs. OUTPUT POWER (DAC TO HP)
MAX9860 toc01
MAX9860
TOTAL HARMONIC DISTORTION + NOISE vs. OUTPUT POWER (DAC TO HP)
MAX9860 toc02
TOTAL HARMONIC DISTORTION + NOISE vs. FREQUENCY (DAC TO HP)
RL = 32 1 THD+N (%)
MAX9860 toc03
10 RL = 32 1 THD+N (%) f = 3.5kHz 0.1 f = 1kHz 0.01 f = 20kHz 0.001 0 5 10 15 20 25
10 RL = 16 1 THD+N (%) f = 3.5kHz 0.1 f = 1kHz 0.01 f = 20kHz 0.001
10
0.1
POUT = 5mW
0.01
POUT = 20mW
0.001 0 10 20 30 40 50 60 0.01 0.1 1 10 OUTPUT POWER (mW) FREQUENCY (kHz)
30
OUTPUT POWER (mW)
TOTAL HARMONIC DISTORTION + NOISE vs. FREQUENCY (DAC TO HP)
MAX9860 toc04
TOTAL HARMONIC DISTORTION + NOISE vs. FREQUENCY (MICL TO ADC)
MAX9860 toc05
TOTAL HARMONIC DISTORTION + NOISE vs. FREQUENCY (MICL TO ADC)
MICPRE = +20dB VIN = 100mVP-P
MAX9860 toc06
10 RL = 16 1 THD+N (%) POUT = 5mW 0.1
10 MICPRE = 0dB VIN = 1VP-P 1
10
1 THD+N (%) 0.1 THD+N (%) 0.1 0.01 POUT = 20mW 0.01 0.01 0.01 0.1 1 FREQUENCY (kHz) 10 100 0.01 0.1 1 FREQUENCY (kHz) 10 100
0.001 0.01 0.1 1 10 FREQUENCY (kHz)
0.001
TOTAL HARMONIC DISTORTION + NOISE vs. FREQUENCY (MICL TO ADC)
MAX9860 toc07
HEADPHONE OUTPUT POWER vs. LOAD RESISTANCE
MAX9860 toc08
POWER-SUPPLY REJECTION RATIO vs. FREQUENCY (DAC TO HP)
-10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120
MAX9860 toc09
10 MICPRE = +30dB VIN = 31VP-P 1 THD+N (%)
60 50 OUTPUT POWER (mW) 40 30 20 10
0
0.1
0.01
0.001 0.01 0.1 1 FREQUENCY (kHz) 10 100
0 0 25 50 75 100 125 150 LOAD RESISTANCE ()
PSRR (dB)
0.01
0.1
1 FREQUENCY (kHz)
10
100
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9
16-Bit Mono Audio Voice Codec MAX9860
Typical Operating Characteristics (continued)
(VAVDD = +1.8V, VDVDD = VDVDDIO = +1.8V, RL = , headphone load (RL) connected between OUTP and OUTN, CREF = 2.2F, CPREG = CREG = 1F, CMICBIAS = 1F AVMICPGA = 0dB, AVPRE = +20dB, MCLK = 13MHz, TA = +25C, unless otherwise noted.)
POWER-SUPPLY REJECTION RATIO vs. FREQUENCY (MIC TO ADC)
0 -10 -20 -30 PSRR (dB) -40 -50 -60 -70 -80 -90 -100 -110 -120 0.01 0.1 1 FREQUENCY (kHz) 10 100
MAX9860 toc10
0dBFS FFT (DAC TO HP)
MAX9860 toc11
-60dBFS FFT (DAC TO HP)
0 OUTPUT AMPLITUDE (dB) -20 -40 -60 -80 -100 -120 -140 MCLK = 13MHz LRCLK = 8kHz PLL DISABLED
MAX9860 toc12
20 0 OUTPUT AMPLITUDE (dB) -20 -40 -60 -80 -100 -120 -140 0 5 10 FREQUENCY (kHz) 15 MCLK = 13MHz LRCLK = 8kHz PLL DISABLED
20
20
0
5
10 FREQUENCY (kHz)
15
20
0dBFS FFT (DAC TO HP)
MAX9860 toc13
-60dBFS FFT (DAC TO HP)
MAX9860 toc14
0dBFS FFT (DAC TO HP AMP)
0 OUTPUT AMPLITUDE (dB) -20 -40 -60 -80 -100 -120 -140 MCLK = 12.288MHz LRCLK = 48kHz PLL DISABLED
MAX9860 toc15
20 0 OUTPUT AMPLITUDE (dB) -20 -40 -60 -80 -100 -120 -140 0 5 10 FREQUENCY (kHz) 15 MCLK = 13MHz LRCLK = 8kHz PLL ENABLED
20 0 OUTPUT AMPLITUDE (dB) -20 -40 -60 -80 -100 -120 -140 MCLK = 13MHz LRCLK = 8kHz PLL ENABLED
20
20
0
5
10 FREQUENCY (kHz)
15
20
0
5
10 FREQUENCY (kHz)
15
20
-60dBFS FFT (DAC TO HP AMP)
MAX9860 toc16
0dBFS FFT (MICL TO ADC)
MAX9860 toc17
-60dBFS FFT (MICL TO ADC)
0 OUTPUT AMPLITUDE (dB) -20 -40 -60 -80 -100 -120 -140 MCLK = 13MHz LRCLK = 8kHz PLL DISABLED
MAX9860 toc18
20 0 OUTPUT AMPLITUDE (dB) -20 -40 -60 -80 -100 -120 -140 0 5 10
MCLK = 12.288MHz LRCLK = 48kHz PLL DISABLED
20 0 OUTPUT AMPLITUDE (dB) -20 -40 -60 -80 -100 -120 -140 MCLK = 13MHz LRCLK = 8kHz PLL DISABLED
20
15
20
0
1
2 FREQUENCY (kHz)
3
4
0
1
2 FREQUENCY (kHz)
3
4
FREQUENCY (kHz)
10
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16-Bit Mono Audio Voice Codec
Typical Operating Characteristics (continued)
(VAVDD = +1.8V, VDVDD = VDVDDIO = +1.8V, RL = , headphone load (RL) connected between OUTP and OUTN, CREF = 2.2F, CPREG = CREG = 1F, CMICBIAS = 1F AVMICPGA = 0dB, AVPRE = +20dB, MCLK = 13MHz, TA = +25C, unless otherwise noted.)
0dBFS FFT (MICL TO ADC)
MAX9860 toc19
MAX9860
-60dBFS FFT (MICL TO ADC)
MAX9860 toc20
0dBFS FFT (MICL TO ADC)
0 OUTPUT AMPLITUDE (dB) -20 -40 -60 -80 -100 -120 -140 MCLK = 12.288MHz LRCLK = 48kHz PLL DISABLED
MAX9860 toc21
20 0 OUTPUT AMPLITUDE (dB) -20 -40 -60 -80 -100 -120 -140 0 1 2 FREQUENCY (kHz) 3 4 MCLK = 13MHz LRCLK = 8kHz PLL ENABLED
20 0 OUTPUT AMPLITUDE (dB) -20 -40 -60 -80 -100 -120 -140 0 1 2 FREQUENCY (kHz) 3 4 MCLK = 13MHz LRCLK = 8kHz PLL ENABLED
20
0
5
10 FREQUENCY (kHz)
15
20
-60dBFS FFT (MICL TO ADC)
MAX9860 toc22
-5dBFS WIDEBAND FFT (DAC TO HP)
MCLK = 13MHz LRCLK = 8kHz PLL DISABLED RL = 32
MAX9860 toc23
-60dBFS WIDEBAND FFT (DAC TO HP)
MCLK = 13MHz LRCLK = 8kHz PLL DISABLED RL = 32
MAX9860 toc24
20 0 OUTPUT AMPLITUDE (dB) -20 -40 -60 -80 -100 -120 -140 0 5 10 FREQUENCY (kHz) 15 MCLK = 12.288MHz LRCLK = 48kHz PLL DISABLED
20 0 OUTPUT AMPLITUDE (dB) -20 -40 -60 -80 -100
20 0 OUTPUT AMPLITUDE (dB) -20 -40 -60 -80 -100
20
0.1
1
10
100
1000
10,000
0.1
1
10
100
1000
10,000
FREQUENCY (kHz)
FREQUENCY (kHz)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX9860 toc25
DAC DIGITAL FILTER FREQUENCY RESPONSE, 8kHz
MAX9860 toc26
ADC DIGITAL FILTER FREQUENCY RESPONSE, 8kHz
0 OUTPUT AMPLITUDE (dBFS) -10 -20 -30 -40 -50 -60 -70 ELLIPTICAL FOR 8kHz GSM WITH NOTCH AT 217Hz 0.01 0.1 1 10
MAX9860 toc27
4.5 4.0 SUPPLY CURRENT (mA) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 1.65 1.70 1.75 1.80 1.85 1.90 IDVDD + IDVDDIO FULL-DUPLEX 8kHz MODE IAVDD
10 0 OUTPUT AMPLITUDE (dBFS) -10 -20 -30 -40 -50 -60 -70 -80 -90 ELLIPTICAL FOR 8kHz GSM WITH NOTCH AT 217Hz 0.01 0.1 1
10
-80 -90 10
1.95
SUPPLY VOLTAGE (V)
FREQUENCY (kHz)
FREQUENCY (kHz)
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11
16-Bit Mono Audio Voice Codec MAX9860
Typical Operating Characteristics (continued)
(VAVDD = +1.8V, VDVDD = VDVDDIO = +1.8V, RL = , headphone load (RL) connected between OUTP and OUTN, CREF = 2.2F, CPREG = CREG = 1F, CMICBIAS = 1F AVMICPGA = 0dB, AVPRE = +20dB, MCLK = 13MHz, TA = +25C, unless otherwise noted.)
HEADPHONE STARTUP WAVEFORM
MAX9860 toc28
HEADPHONE SHUTDOWN WAVEFORM
SDA (2V/div)
MAX9860 toc29
SDA (2V/div)
SPK+ -SPK(1V/div)
SPK+ -SPK(1V/div)
TIME (4ms/div)
TIME (2ms/div)
SOFT-START ADC
MAX9860 toc30
AUTOMATIC GAIN CONTROL THRESHOLDS
0 OUTPUT AMPLITUDE (dBFS) -10 -20 -30 -40 -50 -60 -70 -80
MAX9860 toc31
10
SDA (2V/div)
ADC OUTPUT (500mV/div)
TIME (4ms/div)
-100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 INPUT AMPLITUDE (dBV)
NOISE GATE THRESHOLDS
MAX9860 toc32
TOTAL HARMONIC DISTORTION + NOISE vs. MCLK FREQUENCY, 0dBFS (DAC to HP)
MAX9860 toc33
DYNAMIC RANGE vs. MCLK FREQUENCY, -60dBFS (DAC to HP)
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 10 20 30 40 LRCLK = 8kHz
MAX9860 toc34
0 -10 OUTPUT AMPLITUDE (dBFS) -20 -30 -40 -50 -60 -70 -80 -90 -100
1 LRCLK = 8kHz
0.1 THD+N (%)
0.01
0.001 -80 -60 -40 -20 10 20 30 40 50 60 INPUT AMPLITUDE (dBV) MCLK FREQUENCY (MHz)
DYNAMIC RANGE (dB)
50
60
MCLK FREQUENCY (MHz)
12
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16-Bit Mono Audio Voice Codec
Pin Description
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 -- NAME MICBIAS REG PREG REF AGND AVDD OUTP OUTN SDA SCL DVDDIO DGND DVDD MCLK SDOUT SDIN LRCLK BCLK IRQ MICRN MICRP MICLN MICLP MICGND EP FUNCTION Microphone Bias. +1.55V microphone bias for internal and/or external microphone. An external resistor from 2.2k to 470 should be used to set the microphone current. Bypass to MICGND with a 1F capacitor. Internal Bias. PREG/2 voltage reference. Bypass to AGND with a 1F capacitor (+0.8V). Positive Internal Regulated Supply. Bypass to AGND with a 1F capacitor (+1.6V). Converter Reference (1.23V). Bypass to AGND with a 2.2F capacitor. Analog Ground Analog Power Supply. Bypass to AGND with 10F and 0.1F capacitors. Positive Headphone Output Negative Headphone Output I2C Serial-Data Input/Output I2C Serial-Data Clock Digital Interface Power Supply. Supply for digital audio interface. Bypass to DGND with a 1F capacitor. Digital Ground Digital Core Power Supply. Bypass to DGND with a 1F capacitor. Master Clock Input Serial Audio Interface ADC Data Output Serial Audio Interface DAC Data Input Serial Audio Interface Left/Right Clock Serial Audio Interface Bit Clock Interrupt Request. IRQ is an active-low open drain output. Pull up to DVDDIO with a 10k resistor. Negative Right Microphone Input. AC-couple to low-side of microphone or connect to negative signal. AC-couple to ground for single-ended operation. Positive Right Microphone Input. AC-couple to high-side of microphone or connect to positive signal. AC-couple the signal for single-ended operation. Negative Left Microphone Input. AC-couple to low-side of microphone or connect to negative signal. AC-couple to ground for single-ended operation. Positive Left Microphone Input. AC-couple to high-side of microphone or connect to positive signal. AC-couple the signal for single-ended operation. MICBIAS Ground. Connect to AGND. Exposed Pad. Connect to AGND.
MAX9860
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13
16-Bit Mono Audio Voice Codec MAX9860
Detailed Description
The MAX9860 is a low-power, voiceband, mono audio codec designed to provide a complete audio solution for wireless voice headsets and other mono audio devices. The mono playback path accepts digital audio over a flexible digital audio interface compatible with I2S, TDM, and left-justified audio signals. An oversampling sigmadelta DAC converts an incoming digital data stream to analog audio and outputs through the mono bridge-tied load headphone amplifier. The stereo record path has two microphone inputs with selectable gain. The microphones are powered by an integrated microphone bias. An oversampling sigmadelta ADC converts the microphone signals and outputs the digital bit stream over the digital audio interface. The record path includes automatic gain control (AGC) to optimize the signal level and a noise gate to reduce idle noise. The automatic gain control monitors the outputs of the ADC and makes constant adjustments to the input gain to reduce the dynamic range of the incoming microphone signal by up to 20dB. The noise gate corrects for the increase in noise typically associated with AGC by lowering the gain when there is no audio signal. Integrated digital filtering provides a range of notch and highpass filters for both the playback and record paths to limit undesirable low-frequency signals and GSM transmission noise. The digital filtering provides attenuation of out-of-band energy by up to 76dB, eliminating audible aliasing. A digital sidetone function allows audio from the record path to be summed into the playback path after digital filtering. The MAX9860's flexible clock circuitry utilizes a programmable clock divider and a digital PLL to allow the DAC and ADC to operate at maximum dynamic range for all combinations of master clock (MCLK) and sample rate (LRCLK). Any master clock between 10MHz to 60MHz is supported as are all sample rates from 8kHz to 48kHz. Master and slave mode are supported for maximum flexibility.
I2C Registers
The MAX9860 audio codec is completely controlled through software using an I2C interface. The power-on default setting is software shutdown, requiring that the internal registers be programmed to activate the device. See Table 1 for the device's complete register map.
I2C Slave Address
The MAX9860 responds to the slave address 0x20 for all write commands and 0x21 for all read operations.
14
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16-Bit Mono Audio Voice Codec
Table 1. I2C Register Map
REGISTER STATUS/INTERRUPT Interrupt Status Microphone NG/AGC Readback Interrupt Enable CLOCK CONTROL System Clock Stereo Audio Clock Control High Stereo Audio Clock Control Low DIGITAL AUDIO INTERFACE Interface Interface DIGITAL FILTERING Voice Filter DAC Attenuation ADC Output Levels DAC Gain and 0 Sidetone MICROPHONE LEVEL CONTROL Microphone Gain 0 RESERVED Reserved Microphone AGC Noise Gate, Microphone AGC POWER MANAGEMENT System Shutdown SHDN 0 0 0 DACEN 0 ADCLEN ADCREN 0x10 0x00 R/W 0 AGCSRC 0 0 AGCRLS ANTH 0 0 0 AGCATK AGCTH 0 0 AGCHLD 0x0D 0x0E 0x0F 0x00 0x00 0x00 R/W R/W MICROPHONE AUTOMATIC GAIN CONTROL ADCRL DVG MAS 0 WCI 0 DBCI ABCI AVFLT DVA ADCLL DVST DDLY ADLY HIZ ST TDM 0 BSEL DVFLT 0 0x06 0x07 0x08 0x09 0x0A 0x0B 0x00 0x00 0x00 0x00 0x00 0x00 R/W R/W R/W R/W R/W R/W 0 PLL NLO 0 PSCLK 0 NHI FREQ 16KHZ 0x03 0x04 0x05 0x00 0x00 0x00 R/W R/W R/W ICLD CLD SLD NG ISLD IULK 0 0 ULK 0 0 0 AGC 0 0 0 0 0 0x00 0x01 0x02 -- -- 0x00 R R R/W B7 B6 B5 B4 B3 B2 B1 B0 REGISTER ADDRESS POR R/W
MAX9860
DIGITAL LEVEL CONTROL
PAM
PGAM
0x0C
0x00
R/W
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15
16-Bit Mono Audio Voice Codec MAX9860
Status/Interrupt
Status registers 0x00 and 0x01 are read-only registers that report the status of various device functions. The status register bits are cleared upon a read operation of the status register and are set the next time the event occurs. Register 0x02 determines whether or not the status flags in register 0x00 simultaneously sets IRQ high.
Table 2. Status/Interrupt Registers
REGISTER ADDRESS 0x00 0x01 0x02 B7 CLD ICLD B6 SLD NG ISLD B5 ULK IULK B4 0 0 B3 0 0 B2 0 AGC 0 B1 0 0 B0 0 0
BITS CLD
FUNCTION Clip Detect Flag. Indicates that a signal has become clipped in the ADC or DAC digital signal paths. CLD also indicates that the AGC function, when enabled, has set the microphone PGA to 0dB and no further gain reduction is possible. Slew Level Detect Flag. When volume or gain changes are made, the slewing circuitry smoothly steps through all intermediate settings. When SLD is set high, all slewing has completed and the volume or gain is at its final value. Digital PLL Unlock Flag. Indicates that the digital audio PLL for the ADC or DAC has become unlocked and digital signal data is not reliable. When beginning operation in master mode, this flag goes high and can be cleared by reading the status register. Noise Gate Attenuation. When the noise gate is enabled these bits indicate the current noise gate attenuation. Code 000 001 010 011 100 101 110 111 Attenuation 0dB 1dB 2dB 3dB 6dB 8dB 10dB 12dB
SLD
ULK
NG
AGC
AGC Gain. When the AGC is enabled these bits indicate the AGC controlled level to the MIC preamp. The levels indicated by these bits correspond to the levels defined for the PGAM bits described in register 0x0C.
16
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16-Bit Mono Audio Voice Codec
Clock Control
The MAX9860 can work with a master clock (MCLK) supplied from any system clock within the range of 10MHz to 60MHz. Internally, the MAX9860 requires a 10MHz to 20MHz clock so a prescaler divides by 1, 2, or 4 to create the internal clock (PCLK). PCLK is used to clock all portions of the MAX9860. The MAX9860 is capable of supporting any sample rate from 8kHz to 48kHz, including all common sample rates (8kHz, 16kHz, 24kHz, 32kHz, 44.1kHz, 48kHz). To accommodate a wide range of system architectures, the MAX9860 supports three main clocking modes: Normal Mode: This mode uses a 15-bit clock divider coefficient to set the sample rate relative to the prescaled MCLK input (PCLK). This allows high flexibility in both the MCLK and LRCLK frequencies and can be used in either master or slave mode. Exact Integer Mode: Common MCLK frequencies (12MHz, 13MHz, and 19.2MHz) can be programmed to operate in exact integer mode for both 8kHz and 16kHz sample rates. In these modes, the MCLK and LRCLK rates are selected by using the FREQ and 16KHZ bits instead of the NHI, NLO, and PLL control bits. PLL Mode: When operating in slave mode, a PLL can be enabled to lock onto externally generated LRCLK signals that are asynchronously related to PCLK.
MAX9860
Table 3. Clock Control Registers
REGISTER ADDRESS 0x03 0x04 0x05 B7 0 PLL B6 0 B5 PSCLK NLO B4 B3 0 NHI B2 FREQ B1 B0 16KHZ
BITS
FUNCTION MCLK Prescaler Divides MCLK down to generate a PCLK between 10MHz and 20MHz. 00 = Disable clock for low-power shutdown. 01 = Select if MCLK is between 10MHz and 20MHz. 10 = Select if MCLK is between 20MHz and 40MHz. 11 = Select if MCLK is greater than 40MHz. Integer Clock Mode Enables exact integer mode for three predefined PCLK frequencies. Exact integer mode is normally intended for master mode, but can be enabled in slave mode if the externally supplied LRCLK exactly matches the frequency specified in each mode. 00 = Normal operation (configure clocking with the PLL, NHI, and NLO bits). 01 = Select when PCLK is 12MHz (LRCLK = PCLK/1500 or PCLK/750). 10 = Select when PCLK is 13MHz (LRCLK = PCLK/1625 or PCLK/812.5). 11 = Select when PCLK is 19.2MHz (LRCLK = PCLK/2400 or PCLK/1200). When FREQ 00, the PLL, NHI, and NLO bits are unused. 16kHz Mode When FREQ 00: 0 = LRCLK is exactly 8kHz. 1 = LRCLK is exactly 16kHz. When FREQ = 00, 16KHZ is used to set the AGC clock rate: 0 = Use when LRCLK 24kHz. 1 = Use when LRCLK > 24kHz.
PSCLK[1:0]
FREQ[1:0]
16KHZ
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17
16-Bit Mono Audio Voice Codec MAX9860
Table 3. Clock Control Registers (continued)
BITS FUNCTION PLL Enable 0 = (Valid for slave and master mode)--The frequency of LRCLK is set by the NHI and NLO divider bits. Set PLL = 0 in slave mode only if the externally generated LRCLK can be exactly selected using the LRCLK divider. 1 = (Valid for slave mode only)--Used when the audio master generates an LRCLK not selectable using the LRCLK divider. A digital PLL locks on to the externally supplied LRCLK signal regardless of the MCLK frequency. Rapid Lock Mode To enable rapid lock mode set NHI and NLO to the nearest desired ratio and set NLO[0] = 1 (Register 0x05, bit 0) before setting the PLL mode bit. LRCLK Divider NHI and NLO control a 15-bit clock divider (N). When the PLL = 0 and FREQ = 00, the frequency of LRCLK is determined by the clock divider. See Table 4 for common N values. NHI and NLO N = (65,536 x 96 x fLRCLK)/fPCLK fLRCLK = LRCLK frequency fPCLK = prescaled MCLK internal clock frequency (PCLK)
PLL
Table 4. Common N Values
LRCLK (kHz) MCLK (MHz) 11.2896 12 12.288 13 19.2 24 26 27 PSCLK 01 01 01 01 01 10 10 10 8 116A 1062 1000 F20 A3D 1062 F20 E90 16 22D4 20C5 2000 1E3F 147B 20C5 1E3F 1D21 32 45A9 4189 4000 3C7F 28F6 4189 3C7F 3A41 44.1 6000 5A51 5833 535F 3873 5A51 535F 5048 48 687D 624E 6000 5ABE 3D71 624E 5ABE 5762
Note: Values in bold italics are exact integers that provide maximum full-scale performance.
18
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16-Bit Mono Audio Voice Codec
Digital Audio Interface
The MAX9860's digital audio interface supports a wide range of operating modes to ensure maximum compatibility. See Figures 1 through 4 for timing diagrams. In master mode, the MAX9860 outputs LRCLK and BCLK, while in slave mode, they are inputs. When operating in master mode, BCLK can be configured in a number of ways to ensure compatiblity with other audio devices.
MAX9860
Table 5. Digital Audio Interface Registers
REGISTER ADDRESS 0x06 0x07 BITS MAS B7 MAS 0 B6 WCI 0 B5 DBCI ABCI B4 DDLY ADLY B3 HIZ ST B2 TDM B1 0 BSEL B0 0
WCI
FUNCTION Master Mode 0 = The MAX9860 operates in slave mode with LRCLK and BCLK configured as inputs. 1 = The MAX9860 operates in master mode with LRCLK and BCLK configured as outputs. LRCLK Invert 0 = Left-channel data is input and output while LRCLK is low. 1 = Right-channel data is input and output while LRCLK is low. WCI is ignored when TDM = 1. DAC BCLK Invert (must be set to ABCI) In master and slave mode: 0 = SDIN is latched into the part on the rising edge of BCLK. 1 = SDIN is latched into the part on the falling edge of BCLK. In master mode: 0 = LRCLK changes state following the rising edge of BCLK. 1 = LRCLK changes state following the falling edge of BCLK. DAC Delay Mode 0 = SDIN data is latched on the first BCLK edge following an LRCLK edge. 1 = SDIN data is assumed to be delayed one BCLK cycle so that it is latched on the 2nd BCLK edge following an LRCLK edge (I2S-compatible mode). DDLY is ignored when TDM = 1. SDOUT High-Impedance Mode 0 = SDOUT is set either high or low after all data bits have been transferred out of the part. 1 = SDOUT goes to a high-impedance state after all data bits have been transferred out of the part, allowing SDOUT to be shared by other devices. Use HIZ only when TDM = 1. TDM Mode Select 0 = LRCLK signal polarity indicates left and right audio. 1 = LRCLK is a framing pulse which transitions polarity to indicate the start of a frame of audio data consisting of multiple channels. When operating in TDM mode the left channel is output immediately following the frame sync pulse. If rightchannel data is being transmitted, the 2nd channel of data immediately follows the 1st channel data. ADC BCLK Invert (must be set to DBCI) 0 = SDOUT is valid on the rising edge of BCLK and transitions immediately after the rising edge. 1 = SDOUT is valid on the falling edge of BCLK and transitions immediately after the falling edge.
DBCI
DDLY
HIZ
TDM
ABCI
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19
16-Bit Mono Audio Voice Codec MAX9860
Table 5. Digital Audio Interface Registers (continued)
BITS FUNCTION ADC Delay Mode 0 = SDOUT data is valid on the first BCLK edge following an LRCLK edge. 1 = SDOUT data is delayed one BCLK cycle so that it is valid on the 2nd BCLK edge following an LRCLK edge (I2S-compatible mode). ADLY is ignored when TDM = 1. Stereo Enable 0 = The interface transmits and receives only one channel of data. If right record path is enabled, no data from this channel is transmitted. 1 = The interface operates in stereo. The left and right incoming data are summed to mono and then routed to the DAC. The summed data is divided by 2 to prevent overload. Both the left and right record signals are transmitted. BCLK Select Configures BCLK when operating in master mode. BSEL has no effect in slave mode. Set BSEL = 010, unless sharing the bus with multiple devices. 000 = Off 001 = 64x LRCLK (192x internal clock divided by 3) 010 = 48x LRCLK (192x internal clock divided by 4) 011 = Reserved for future use. 100 = PCLK/2 101 = PCLK/4 110 = PCLK/8 111 = PCLK/16
ADLY
ST
BSEL
20
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16-Bit Mono Audio Voice Codec MAX9860
AUDIO MASTER MODES (ST = 1): LEFT JUSTIFIED : WCI = 0, _BCI = 0, _DLY = 0 7ns (typ) LRCLK RELATIVE TO PCLK (NOTE 7) SDOUT D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 40ns (max) 0ns (min) BCLK 25ns (min) SDIN 0ns (min) CONFIGURED BY BSEL 7ns (typ) 7ns (typ) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 LEFT 1/f S 7ns (typ) RIGHT
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LEFT JUSTIFIED + LRCLK INVERT: WCI = 1, _BCI = 0, _DLY = 0 7ns (typ) LRCLK RELATIVE TO PCLK (NOTE 7) SDOUT D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 40ns (max) 0ns (min) BCLK 25ns (min) SDIN 0ns (min) CONFIGURED BY BSEL D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 RIGHT 1/fS 7ns (typ) LEFT
7ns (typ)
7ns (typ)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LEFT JUSTIFIED + BCLK INVERT: WCI = 0, _BCI = 1, _DLY = 0 7ns (typ) LRCLK RELATIVE TO PCLK (NOTE 7) SDOUT D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 40ns (max) 0ns (min) BCLK 25ns (min) SDIN 0ns (min) CONFIGURED BY BSEL 7ns (typ) 7ns (typ) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 LEFT 1/f S 7ns (typ) RIGHT
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
I2S: WCI = 0, _BCI = 0, _DLY = 1 7ns (typ) LRCLK RELATIVE TO PCLK (NOTE 7) SDOUT D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 40ns (max) 0ns (min) BCLK 25ns (min) SDIN 0ns (min) CONFIGURED BY BSEL 7ns (typ) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 LEFT 1/fS 7ns (typ) RIGHT
7ns (typ)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
NOTE 7: THE DELAY FROM A BCLK EDGE AND AN LRCLK EDGE IS DETERMINED BY LENGTH OF TIME THAT PCLK (THE INTERNALLY DIVIDED DOWN VERSION OF MCLK AS DEFINED BY THE PSCLK BITS) IS HIGH DURING ONE PERIOD OF MCLK PLUS THE INTERNAL DELAY. FOR EXAMPLE: IF PCLK = 12.288MHz, THE DELAY BETWEEN BCLK AND LRCLK IS TYPICALLY 45ns.
Figure 1. Digital Audio Interface Audio Master Mode Examples
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21
16-Bit Mono Audio Voice Codec MAX9860
VOICE (TDM) MASTER MODES: _BCI = 0, HIZ = 1, ST = 0 7ns (typ) LRCLK 1/fS RELATIVE TO PCLK (NOTE 8) SDOUT L15 L14 L13 L12 L11 L10 L9 L8 L7 40ns (max) 0ns (min) BCLK 25ns (min) SDIN 0ns (min) CONFIGURED BY BSEL L6 L5 L4 L3 L2 L1 L0 7ns (typ)
7ns (typ)
7ns (typ)
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4
L3 L2 L1 L0
_BCI = 1, HIZ = 1, ST = 0 7ns (typ) LRCLK 1/fS RELATIVE TO PCLK (NOTE 8) SDOUT L15 L14 L13 L12 L11 L10 L9 L8 40ns (max) 0ns (min) BCLK 25ns (min) SDIN 0ns (min) CONFIGURED BY BSEL L7 L6 L5 L4 L3 L2 L1 L0 7ns (typ)
7ns (typ)
7ns (typ)
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4
L3 L2 L1 L0
_BCI = 0, HIZ = 0, ST = 0 7ns (typ) LRCLK 1/fS RELATIVE TO PCLK (NOTE 8) SDOUT L15 L14 L13 L12 L11 L10 L9 L8 40ns (max) 0ns (min) BCLK 25ns (min) SDIN 0ns (min) CONFIGURED BY BSEL L7 L6 L5 L4 L3 L2 L1 L0 7ns (typ)
7ns (typ)
7ns (typ)
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4
L3 L2 L1 L0
_BCI = 0, HIZ = 1, ST = 1 7ns (typ) LRCLK 1/fS RELATIVE TO PCLK (NOTE 8) SDOUT L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 40ns (max) 0ns (min) BCLK 25ns (min) SDIN 0ns (min) L15 L14 L13 L12 L11 L10 L9 L8 L7 CONFIGURED BY BSEL L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 7ns (typ)
7ns (typ)
7ns (typ)
L6 L5 L4 L3 L2 L1
L0 R15 R14 R13 R12 R11 R10 R9
R8 R7 R6 R5 R4 R3 R2 R1 R0
NOTE 8: THE DELAY FROM A BCLK EDGE AND AN LRCLK EDGE IS DETERMINED BY LENGTH OF TIME THAT PCLK (THE INTERNALLY DIVIDED DOWN VERSION OF MCLK AS DEFINED BY THE PSCLK BITS) IS HIGH DURING ONE PERIOD OF MCLK PLUS THE INTERNAL DELAY. FOR EXAMPLE: IF PCLK = 12.288MHz, THE DELAY BETWEEN BCLK AND LRCLK IS TYPICALLY 45ns.
Figure 2. Digital Audio Interface Voice Master Mode Examples
22
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16-Bit Mono Audio Voice Codec MAX9860
AUDIO SLAVE MODES (ST = 1): LEFT JUSTIFIED: WCI = 0, _BCI = 0, _DLY = 0 LRCLK 25ns (min) SDOUT D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 40ns (max) 0ns (min) BCLK 25ns (min) SDIN 0ns (min) 75ns (min) 30ns (min) D15 LEFT 1/fS 0ns (min) D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 RIGHT
30ns (min)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LEFT JUSTIFIED + LRCLK INVERT: WCI = 1, _BCI = 0, _DLY = 0 LRCLK 25ns (min) SDOUT D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 40ns (max) 0ns (min) 30ns (min) 75ns (min) D15 RIGHT 1/fS 0ns (min) D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 LEFT
BCLK 25ns (min) SDIN 0ns (min)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 LEFT JUSTIFIED + BCLK INVERT: WCI = 0, _BCI = 1, _DLY = 0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LRCLK 25ns (min) SDOUT D15
LEFT 1/fS
RIGHT 0ns (min) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 40ns (max) 0ns (min) 30ns (min)
BCLK 25ns (min) SDIN 0ns (min) 75ns (min)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
I2S: WCI = 0, _BCI = 0, _DLY = 1 LRCLK 25ns (min) SDOUT D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 40ns (max) 0ns (min) BCLK 25ns (min) SDIN 0ns (min) 75ns (min) D15 LEFT 1/fS 0ns (min) D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 RIGHT
30ns (min)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Figure 3. Digital Audio Interface Audio Slave Mode Examples
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23
16-Bit Mono Audio Voice Codec MAX9860
VOICE (TDM) SLAVE MODES: _BCI = 0, HIZ =1, ST = 0 LRCLK 1/fS 25ns (min) SDOUT L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 40ns (max) 0ns (min) BCLK 25ns (min) SDIN 0ns (min) L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 _BCI = 1, HIZ = 1, ST = 0 LRCLK 1/fS 25ns (min) SDOUT L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 40ns (max) 0ns (min) BCLK 25ns (min) SDIN 0ns (min) L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 _BCI = 0, HIZ = 0, ST = 0 LRCLK 1/fS 25ns (min) SDOUT L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 40ns (max) 0ns (min) BCLK 25ns (min) SDIN 0ns (min) L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 _BCI = 0, HIZ = 1, ST = 1 LRCLK 1/fS 25ns (min) SDOUT L15 L14 L13 L12 L11 L10 L9 L8 L7 40ns (max) 0ns (min) BCLK 25ns (min) SDIN 0ns (min) 75ns (min) L6 L5 L4 L3 L2 L1 30ns (min) 0ns (min) 0ns (min) L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 75ns (min) L3 L2 L1 L0 0ns (min) 0ns (min) 75ns (min) L3 L2 L1 L0 0ns (min) 0ns (min) 75ns (min) 30ns (min) L2 L1 L0 0ns (min) 0ns (min)
L5 L4 L3 L2 L1 L0
30ns (min)
L5 L4 L3 L2 L1 L0
30ns (min)
L5 L4 L3 L2 L1 L0
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3
L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
Figure 4. Digital Audio Interface Voice Slave Mode Examples
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16-Bit Mono Audio Voice Codec
Digital Filtering
The MAX9860 incorporates selecable highpass and notch filters for both the playback and record paths. Each filter is valid for a specific sample rate.
MAX9860
Table 6. Digital Filter Registers
REGISTER ADDRESS 0x08 BITS AVFLT DVFLT B7 B6 AVFLT FUNCTION ADC Voice Filter Frequency Select. See Table 7. DAC Voice Filter Frequency Select. See Table 7. B5 B4 B3 B2 DVFLT B1 B0
Table 7. Digital Filters
CODE 0x0 0x1 0x2 0x3 0x4 0x5 0x6 to 0xF FILTER TYPE -- Elliptical Butterworth Elliptical Butterworth Butterworth -- SAMPLE RATE -- 16kHz 16kHz 8kHz 8kHz 48kHz -- Disabled Elliptical highpass with 217Hz notch 500Hz Butterworth highpass Elliptical highpass with 217Hz notch 500Hz Butterworth highpass 200Hz Butterworth highpass Reserved DESCRIPTION
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16-Bit Mono Audio Voice Codec MAX9860
Digital Level Control
The MAX9860 includes digital gain adjustment for the playback and record paths. Independent gain adjustment is provided for the two record channels. Sidetone gain adjustment is also provided to set the sidetone level relative to the playback level.
Table 8. Digital Level Control Registers
REGISTER ADDRESS 0x09 0x0A 0x0B BITS B7 B6 ADCRL DVG FUNCTION DAC Level Adjust Adjusts the digital audio level before being converted by the DAC. The least significant bit of DVA is always 0. CODE GAIN CODE GAIN CODE GAIN 0x00 +3 0x40 -29 0x80 -61 0x02 +2 0x42 -30 0x82 -62 0x04 +1 0x44 -31 0x84 -63 0x06 0 0x46 -32 0x86 -64 0x08 -1 0x48 -33 0x88 -65 0x0A -2 0x4A -34 0x8A -66 0x0C -3 0x4C -35 0x8C -67 0x0E -4 0x4E -36 0x8E -68 0x10 -5 0x50 -37 0x90 -69 0x12 -6 0x52 -38 0x92 -70 0x14 -7 0x54 -39 0x94 -71 0x16 -8 0x56 -40 0x96 -72 0x18 -9 0x58 -41 0x98 -73 0x1A -10 0x5A -42 0x9A -74 0x1C -11 0x5C -43 0x9C -75 0x1E -12 0x5E -44 0x9E -76 0x20 -13 0x60 -45 0xA0 -77 0x22 -14 0x62 -46 0xA2 -78 0x24 -15 0x64 -47 0xA4 -79 0x26 -16 0x66 -48 0xA6 -80 0x28 -17 0x68 -49 0xA8 -81 0x2A -18 0x6A -50 0xAA -82 0x2C -19 0x6C -51 0xAC -83 0x2E -20 0x6E -52 0xAE -84 0x30 -21 0x70 -53 0xB0 -85 0x32 -22 0x72 -54 0xB2 -86 0x34 -23 0x74 -55 0xB4 -87 0x36 -24 0x76 -56 0xB6 -88 0x38 -25 0x78 -57 0xB8 -89 0x3A -26 0x7A -58 0xBA -90 0x3C -27 0x7C -59 0xBC MUTE 0x3E -28 0x7E -60 -- -- B5 B4 DVA ADCLL DVST 0 B3 B2 B1 B0
DVA
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16-Bit Mono Audio Voice Codec MAX9860
Table 8. Digital Level Control Registers (continued)
BITS FUNCTION Left and Right ADC Output Level Adjusts the digital audio level output by the ADCs. CODE GAIN 0x0 +3 0x1 +2 0x2 +1 0x3 0 0x4 -1 0x5 -2 0x6 -3 0x7 -4 0x8 -5 0x9 -6 0xA -7 0xB -8 0xC -8 0xD -10 0xE -11 0xF -12 DAC Gain The gain set by DVG adds to the level set by DVA. CODE GAIN 00 0 01 +6 10 +12 11 +18 Sidetone Sets the level of left ADC output mixed into the DAC. CODE GAIN CODE 0x00 Disabled 0x10 0x01 0 0x11 0x02 -2 0x12 0x03 -4 0x13 0x04 -6 0x14 0x05 -8 0x15 0x06 -10 0x16 0x07 -12 0x17 0x08 -14 0x18 0x09 -16 0x19 0x0A -18 0x1A 0x0B -20 0x1B 0x0C -22 0x1C 0x0D -24 0x1D 0x0E -26 0x1E 0x0F -28 0x1F
ADCRL/ADCLL
DVG
DVST
GAIN -30 -32 -34 -36 -38 -40 -42 -44 -46 -48 -50 -52 -54 -56 -58 -60
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27
16-Bit Mono Audio Voice Codec MAX9860
Microphone Inputs
The MAX9860 provides two differential microphone inputs and a low-noise 1.55V microphone bias for powering the microphones. In typical applications, the left microphone is used to record a voice signal and the right microphone is used to record a background noise signal. In applications that require only one microphone, use the left microphone input and disable the right ADC. The microphone signals are amplified by two stages of gain and then routed to the ADCs. The first stage offers selectable 0dB, 20dB, or 30dB settings. The second stage is a programmable gain amplifier (PGA) adjustable from 0dB to 20dB in 1dB steps. Zero-crossing detection is included on the PGA to minimize zipper noise while making gain changes. See Figure 5 for a detailed diagram of the microphone input structure.
MICBIAS
1.55V
REG
MAX9860
0/20/30dB VCM 0dB to +20dB PGA ADC L
MICLP MICLN PREAMP
MICGND AGC 0/20/30dB VCM MICRP MICRN PREAMP PGA 0dB to +20dB ADC R
Figure 5. Microphone Input Block Diagram
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16-Bit Mono Audio Voice Codec MAX9860
Table 9. Microphone Input Register
REGISTER ADDRESS 0x0C B7 0 B6 PAM B5 B4 B3 B2 PGAM B1 B0
BITS
PAM
PGAM
FUNCTION Left and Right Microphone Preamp Gain CODE GAIN (dB) 00 Disabled 01 0 10 +20 11 +30 Note: Selecting 00 disables the microphone inputs and microphone bias automatically. Left and Right Microphone PGA CODE GAIN (dB) CODE GAIN (dB) 0x00 +20 0x0B +9 0x01 +19 0x0C +8 0x02 +18 0x0D +7 0x03 +17 0x0E +6 0x04 +16 0x0F +5 0x05 +15 0x10 +4 0x06 +14 0x11 +3 0x07 +13 0x12 +2 0x08 +12 0x13 +1 0x09 +11 0x14 0 0x0A +10 -- -- Note: When AGC is enabled, the AGC controller overrides these settings.
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29
16-Bit Mono Audio Voice Codec MAX9860
Automatic Gain Control (AGC) and Noise Gate
The MAX9860 includes AGC on both microphone inputs. AGC is enabled by setting the hold time through AGCHLD. AGC dynamically controls the analog PGA microphone input gain to hold the level constant over a 20dB input range, enhancing the voice path operation for various use conditions. When AGC is enabled, it monitors the signal level at the output of the ADC and then makes gain adjustments by controlling the analog microphone PGA. When AGC is enabled, PGAM is not user programmable. Since AGC increases the level of all signals below a user-defined threshold, the noise floor effectively is increased by 20dB. To counteract this, a noise gate is included to reduce the gain at low levels. Unlike typical noise gates that completely silence the output below a threshold, the noise gate in the MAX9860 reduces the gain for signals below the defined level. As the signal level becomes further below the threshold, the gain is further reduced. The Automatic Gain Control Thresholds and Noise Gate Thresholds graphs in the Typical Operating Characteristics show the resulting steady-state transfer curves when AGC and the noise gate are enabled.
Table 10. AGC and Noise Gate Registers
REGISTER ADDRESS 0x0E 0x0F BITS AGCSRC B7 AGCSRC B6 B5 AGCRLS ANTH B4 B3 AGCATK AGCTH FUNCTION AGC/Noise Gate Signal Source Select 0 = The left ADC output is used by the AGC and noise gate. 1 = The sum of the left and right ADC outputs is used by the AGC and noise gate. AGC Release Time Time taken by the AGC circuit to increase the gain from minimum to maximum. CODE TIME 000 78ms 001 156ms 010 312ms 011 625ms 100 1.25s 101 2.5s 110 5s 111 10s AGC Attack Time The time constant of the AGC gain reduction curve. CODE TIME (ms) 00 3 01 12 10 50 11 200 AGC Hold Time Time the AGC circuit waits before beginning to increase gain when a signal below the threshold is detected. CODE TIME (ms) 00 AGC disabled 01 50 10 100 11 400 B2 B1 AGCHLD B0
AGCRLS
AGCATK
AGCHLD
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16-Bit Mono Audio Voice Codec MAX9860
Table 10. AGC and Noise Gate Registers (continued)
BITS FUNCTION Noise Gate Threshold The signal level at which the noise gate begins reducing the gain. When the signal level is above the threshold the noise gate has no effect. When the signal level is below the threshold, the noise gate decreases the gain by 1dB for every 2dB the signal is below the threshold. The noise gate can be enabled independently from AGC. When AGC is enabled, PGAM must be set to +20dB (indicating a small signal is present) for the noise gate to attenuate. For microphone signals, use the noise gate and AGC simultaneously with ANTH set between -16dB and -28dB. ANTH[3:0] LEVEL (dBFS) ANTH[3:0] LEVEL (dBFS) 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 Disabled -72 -68 -64 -60 -56 -52 -48 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF -44 -40 -36 -32 -28 -24 -20 -16
ANTH
AGC Signal Threshold The target output signal level. When the signal level is below the threshold, the AGC increases the gain. The signal level is measured after ADCRL and ADCLL are applied to the ADC output. ANTH[3:0] LEVEL (dBFS) ANTH[3:0] LEVEL (dBFS) 0x0 0x1 AGCTH 0x2 0x3 0x4 0x5 0x6 0x7 -3 -4 -5 -6 -7 -8 -9 -10 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF -11 -12 -13 -14 -15 -16 -17 -18
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16-Bit Mono Audio Voice Codec MAX9860
Power Management
The MAX9860 includes complete power management control to minimize power usage. The DAC and both ADCs can be independently enabled so that only the required circuitry is active.
Table 11. Power Management Register
REGISTER ADDRESS 0x10 BITS Active-Low Software Shutdown 0 = MAX9860 is in full shutdown. 1 = MAX9860 is powered on. When SHDN = 0. All register settings are preserved and the I2C interface remains active. DAC Enable 0 = DAC disabled. 1 = DAC enabled. ADC Left/Right Enable 0 = Left/right ADC enabled. 1 = Left/right ADC disabled. The left ADC must be enabled when using the right ADC. B7 SHDN B6 0 B5 0 B4 0 B3 DACEN B2 0 B1 ADCLEN B0 ADCREN
FUNCTION
SHDN
DACEN
ADCLEN/ADCREN
Revision Code
The MAX9860 includes a revision code to allow easy identification of the device revision. The current revision code is 0x40.
Table 12. Revision Code Register
ADDR 0xFF B7 B6 B5 B4 REV B3 B2 B1 B0
I2C Serial Interface
The MAX9860 features an 2-wire serial interface consisting of a serial-data line (SDA) and a serial-clock line (SCL). SDA and SCL facilitate communication between the MAX9860 and the master at clock rates up to 400kHz. Figure 6 shows the 2-wire interface timing diagram. The master generates SCL and initiates data transfer on the bus. The master device writes data to the MAX9860 by transmitting the proper slave address followed by the register address and then the data word. Each transmit sequence is framed by a START (S) or REPEATED START (Sr) condition and a STOP (P) condition. Each word transmitted to the MAX9860 is 8 bits long and is followed by an acknowledge clock pulse. A master reading data from the MAX9860 transmits the proper slave address followed by a series of nine SCL pulses. The MAX9860
SMBus is a trademark of Intel Corp.
32
I2C/SMBusTM-compatible,
transmits data on SDA in sync with the master-generated SCL pulses. The master acknowledges receipt of each byte of data. Each read sequence is framed by a START or REPEATED START condition, a not acknowledge, and a STOP condition. SDA operates as both an input and an open-drain output. A pullup resistor, typically greater than 500, is required on SDA. SCL operates only as an input. A pullup resistor, typically greater than 500, is required on SCL if there are multiple masters on the bus, or if the single master has an opendrain SCL output. Series resistors in line with SDA and SCL are optional. Series resistors protect the digital inputs of the MAX9860 from high voltage spikes on the bus lines, and minimize crosstalk and undershoot of the bus signals.
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16-Bit Mono Audio Voice Codec MAX9860
SDA tSU,STA tHD,DAT tHIGH tBUF tHD,STA tSP tSU,STO
tLOW
tSU,DAT
SCL tHD,STA tR START CONDITION
tF REPEATED START CONDITION STOP CONDITION START CONDITION
Figure 6. 2-Wire Interface Timing Diagram
Bit Transfer One data bit is transferred during each SCL cycle. The data on SDA must remain stable during the high period of the SCL pulse. Changes in SDA while SCL is high are control signals (see the START and STOP Conditions section). START and STOP Conditions SDA and SCL idle high when the bus is not in use. A master initiates communication by issuing a START (S) condition. A START condition is a high-to-low transition on SDA with SCL high. A STOP (P) condition is a low-tohigh transition on SDA while SCL is high (Figure 7). A START condition from the master signals the beginning of a transmission to the MAX9860. The master terminates transmission, and frees the bus, by issuing a STOP condition. The bus remains active if a REPEATED START (Sr) condition is generated instead of a STOP condition. Early STOP Conditions The MAX9860 recognizes a STOP condition at any point during data transmission except if the STOP condition occurs in the same high pulse as a START condition. For proper operation, do not send a STOP condition during the same SCL high pulse as the START condition. Slave Address The slave address is defined as the seven most significant bits (MSBs) followed by the read/write bit. For the MAX9860, the seven most significant bits are 0010000. Setting the read/write bit to 1 (slave address = 0x21) configures the MAX9860 for read mode. Setting the read/write bit to 0 (slave address = 0x20) configures the MAX9860 for write mode. The address is the first byte of information sent to the MAX9860 after the START condition.
Acknowledge The acknowledge bit (ACK) is a clocked 9th bit that the MAX9860 uses to handshake receipt each byte of data when in write mode (see Figure 7). The MAX9860 pulls down SDA during the entire master-generated 9th clock pulse if the previous byte is successfully received. Monitoring ACK allows for detection of unsuccessful data transfers. An unsuccessful data transfer occurs if a receiving device is busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the bus master retries communication. The master pulls down SDA during the 9th clock cycle to acknowledge receipt of data when the MAX9860 is in read mode. An acknowledge is sent by the master after each read byte to allow data transfer to continue. A not acknowledge is sent when the master reads the final byte of data from the MAX9860, followed by a STOP condition. Write Data Format A write to the MAX9860 includes transmission of a START condition, the slave address with the R/W bit set to 0, one byte of data to configure the internal register address pointer, one or more bytes of data, and a STOP condition. Figure 9 illustrates the proper frame format for writing one byte of data to the MAX9860. Figure 10 illustrates the frame format for writing n bytes of data to the MAX9860. The slave address with the R/W bit set to 0 indicates that the master intends to write data to the MAX9860. The MAX9860 acknowledges receipt of the address byte during the master-generated 9th SCL pulse. The second byte transmitted from the master configures the MAX9860's internal register address pointer. The pointer tells the MAX9860 where to write the next byte of data. An acknowledge pulse is sent by the MAX9860 upon receipt of the address pointer data.
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33
16-Bit Mono Audio Voice Codec MAX9860
S
Sr
P
SCL
SDA
Figure 7. START (S), STOP (P), and REPEATED START (Sr) Conditions
START CONDITION SCL 1 28
CLOCK PULSE FOR ACKNOWLEDGMENT
9 NOT ACKNOWLEDGE
SDA ACKNOWLEDGE
Figure 8. Acknowledge
ACKNOWLEDGE FROM MAX9860 B7 ACKNOWLEDGE FROM MAX9860 S SLAVE ADDRESS R/W 0 A ACKNOWLEDGE FROM MAX9860 REGISTER ADDRESS A DATA BYTE 1 BYTE AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER A P B6 B5 B4 B3 B2 B1 B0
Figure 9. Writing One Byte of Data to the MAX9860
The third byte sent to the MAX9860 contains the data that is written to the chosen register. An acknowledge pulse from the MAX9860 signals receipt of the data byte. The address pointer autoincrements to the next register address after each received data byte. This autoincrement feature allows a master to write to sequential registers within one continuous frame. Figure 10 illustrates how to write to multiple registers with one frame. The master signals the end of transmission by issuing a STOP condition. Register addresses greater than 0x10 are reserved. Do not write to these addresses.
34
Read Data Format Send the slave address with the R/W bit set to 1 to initiate a read operation. The MAX9860 acknowledges receipt of its slave address by pulling SDA low during the 9th SCL clock pulse. A START command followed by a read command resets the address pointer to register 0x00. The first byte transmitted from the MAX9860 is the contents of register 0x00. Transmitted data is valid on the rising edge of SCL. The address pointer autoincrements after each read data byte. This autoincrement
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16-Bit Mono Audio Voice Codec MAX9860
ACKNOWLEDGE FROM MAX9860 ACKNOWLEDGE FROM MAX9860 S SLAVE ADDRESS R/W 0 ACKNOWLEDGE FROM MAX9860 A REGISTER ADDRESS A B7 B6 B5 B4 B3 B2 B1 B0 ACKNOWLEDGE FROM MAX9860 B7 B6 B5 B4 B3 B2 B1 B0
DATA BYTE 1 1 BYTE
A
DATA BYTE n 1 BYTE
A
P
AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER
Figure 10. Writing N Bytes of Data to the MAX9860
NOT ACKNOWLEDGE FROM MASTER ACKNOWLEDGE FROM MAX9860 S SLAVE ADDRESS R/W 0 A ACKNOWLEDGE FROM MAX9860 REGISTER ADDRESS A ACKNOWLEDGE FROM MAX9860 Sr SLAVE ADDRESS R/W 1 A DATA BYTE 1 BYTE AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER A P
REPEATED START
Figure 11. Reading One Byte of Data from the MAX9860
ACKNOWLEDGE FROM MAX9860 S SLAVE ADDRESS R/W 0 A
ACKNOWLEDGE FROM MAX9860 REGISTER ADDRESS A
ACKNOWLEDGE FROM MAX9860 Sr SLAVE ADDRESS R/W 1 A DATA BYTE 1 BYTE AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER A P
REPEATED START
Figure 12. Reading N Bytes of Data from the MAX9860
feature allows all registers to be read sequentially within one continuous frame. A STOP (P) condition can be issued after any number of read data bytes. If a STOP condition is issued followed by another read operation, the first data byte to be read is from register 0x00. The address pointer can be preset to a specific register before a read command is issued. The master presets the address pointer by first sending the MAX9860's slave address with the R/W bit set to 0 followed by the register address. A REPEATED START (Sr) condition is then sent followed by the slave address with the R/W bit set to 1. The MAX9860 then transmits the contents of the specified register. The address pointer autoincrements after transmitting the first byte.
The master acknowledges receipt of each read byte during the acknowledge clock pulse. The master must acknowledge all correctly received bytes except the last byte. The final byte must be followed by a not acknowledge from the master and then a STOP condition. Figure 11 illustrates the frame format for reading one byte from the MAX9860. Figure 12 illustrates the frame format for reading multiple bytes from the MAX9860.
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35
16-Bit Mono Audio Voice Codec MAX9860
Pin Configuration
MICRN MICLN MICRP MICLP
TOP VIEW
24 MICBIAS REG PREG REF AGND AVDD 1 + 2 3 4 5 6 7 OUTP
23
22
21
20
19 18 17 16 BCLK LRCLK SDIN SDOUT MCLK DVDD
MAX9860
*EP
15 14 13
Route microphone signals from the microphone to the MAX9860 as a differential pair, ensuring that the positive and negative signals follow the same path as closely as possible with equal trace length. When using singleended microphones or other single-ended audio sources, AC ground the negative microphone input signal as near to the audio source as possible and then treat the positive and negative traces as differential pairs. The MAX9860 thin QFN package features an exposed thermal pad on its underside. This pad lowers the package's thermal resistance by providing a direct heat conduction path from the die to the PCB. Connect the exposed thermal pad to AGND. An evaluation kit (EV kit) is available to provide an example layout for the MAX9860. The EV kit allows quick setup of the MAX9860 and includes easy-to-use software allowing all internal registers to be controlled.
MICGND
8 OUTN
9 SDA
10 SCL
11 DVDDIO
12 DGND
THIN QFN 4mm x 4mm
*EP = EXPOSED PAD
Applications Information
Proper layout and grounding are essential for optimum performance. When designing a PCB for the MAX9860, partition the circuitry so that the analog sections of the MAX9860 are separated from the digital sections. This ensures that the analog audio traces do not need to be routed near digital traces. Use a large continuous ground plane on a dedicated layer of the PCB to minimize loop areas. Connect AGND, DGND, and MICGND directly to the ground plane using the shortest trace length possible. Proper grounding improves audio performance, minimizes crosstalk between channels, and prevents any digital noise from coupling into the analog audio signal. Ground the bypass capacitors on REG, PREG, and REF directly to the ground plane with minimum trace length. Also be sure to minimize the path length to AGND and MICGND. Bypass AVDD directly to AGND. Bypass MICBIAS directly to MICGND. Connect all digital I/O termination to the ground plane with minimum path length to DGND. Bypass DVDD and DVDDIO directly to DGND.
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IRQ
16-Bit Mono Audio Voice Codec
Functional Diagram/Typical Operating Circuit
1.7V TO 3.6V 1.7V TO 1.9V 1.7V TO 1.9V
MAX9860
1F 11 DVDDIO 13 DVDD
1F 6 AVDD DIGITAL ANALOG
0.1F
10F
SDOUT 15 MONO DIGITAL AUDIO INTERFACE LRCLK 17
0, +6dB, +12dB, +24dB DVG P P
-90dB TO 0 DVA INTERPOLATION FILTER P P 0, 20dB, 30dB PAM DAC
7 OUTP
SDIN 16
8 P
OUTN
BCLK 18 P DVDDIO P P IRQ 19 MCLK 14 DVDDIO TIMING AND CONTROL LOGIC
DVST -60dB TO 0dB (2dB STEPS) -12dB TO +3dB ADCLL/ ADCRL P LOW-LEVEL AUDIO QUIETING CONTROL P P
MAX9860
LEFT ADC DECIMATION FILTER P RIGHT ADC
0 TO +20dB (1dB STEPS) PGAM
1F 23 MICLP 22 MICLN 1F 1F 21 MICRP 20 MICRN P MICBIAS 1 MICBIAS 2.2F 1F
10k
P 0 TO +20dB (1dB STEPS) PGAM
0, P 20dB, 30dB PAM
1.5k
1.5k SCL 10 SDA 9 I2C SERIAL PORT STATUS
AUTOMATIC GAIN CONTROL P
P
P USERPROGRAMMABLE MODE CONTROL DGND 12 AGND 5 MICGND 24 1F
INTERNAL REGULATORS REG 2 1F PREG 3 2.2F REF 4
P INDICATES USER PROGRAMMABLE I2C CONTROL BITS.
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37
16-Bit Mono Audio Voice Codec MAX9860
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PACKAGE TYPE 24 TQFN-EP PACKAGE CODE T2444+4 DOCUMENT NO. 21-0139
24L QFN THIN.EPS
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16-Bit Mono Audio Voice Codec
Package Information (continued)
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages.
MAX9860
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 39
(c) 2008 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.

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